For HI3521DV100 HI3521 Plus Development Board 8-way 5MP AHD TVI CVI Audio | Компьютеры и офис


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For HI3521DV100 HI3521 Plus Development Board 8-way 5MP AHD TVI CVI Audio | Компьютеры и

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HI3521DV100 HI3521 Plus Development Plate 5MP AHD TVI CVI

Hi35xx NVR DVR Series SoC Handbook

Link: //pan.baidu.com/s/1DolEGgtDezBhgUtE9DbhHQ

Extract code: 58W8


Standard Package:

Motherboard + power adapter +USB to serial line +SATA line + hard disk power line to send AHD camera module +BNC transmission line (a set of hands can directly develop new products)


8 way AHD 1080P or 8 way AHD 720P or 8 way CVBS input HDMI VGAFT encoding to protect EF264 or H265 format video files;Source code available

Support 1 way local H264 or H265 video file decoding playback,HDMI VGAR source output can be double speed playback, slow playback, now pause, etc., provide source code.

3521DV100 development board interface description

01 USB interface X2 can be connected with mouse, keyboard, WiFi.4G module and other USB devices

02 Power interface x 1 12V DC power supply

SATA interface X2 2-way hard disk interface

Ethernet interface X1 standard Ethernet interface, feed cable

X1 VGA and HDMI homologous output

06 HDMI output interface

1 VGA and IDMI homologous output X1 and 1-way hard disk power interface

08 serial port (TTL) interface X1 TTL level serial port console;

09 Audio Input Interface X1 Audio Input Interface

Audio output interface X1 Audio output

11 BNC video input interface X8 AHD, CVBS camera video input interface

12 idle GPIO interface X7 7 idle GPIOs, 2 of which can be reused as a serial port


Hi3521DV100 development board parameters

The processor ARM A7 dual-core @MAX1.3GHz

DDR memory 8G bit

AD chip NVP6158C X 2

Supports H265 P24 LDFEC format

Video input up to 8-way AHD camera

Video output VGA and HDMI homologous output

Video storage 2-way SATA hard disk interface

Hi3521DV100 Plus development board information description

01 AHD 5MP camera real-time display source code can be viewed through the VGA, HDM1 screen real-time 8 way AHD 5MP camera surveillance video 02 AHD 5MP camera real-time coding save source code at the same time 8 way AHD 5MP camera surveillance video encoding saved as a local file, support H265,H264 format

03 AHD/TVI/CVI 4MP camera real-time display source code can be viewed through the VGA, HDMI screen real-time 8 way AHD/TVI/CVI 4MP camera surveillance video

04 AHD TVI/CVI 4 mp camera/keep real-time encoding source also will be 8 road AHD/TVI/CVI 4 mp camera surveillance video coding is saved as a local file, support H265. | H264 format

05 AHD/TV1/CVI 1080P camera real-time display source code can be viewed through the VGA, HDMI screen real-time 8 way AHD/TV1/CVI 1080P camera surveillance video

06 AHD/TVI/CVI 1080P camera real-time coding save source H264 format at the same time 8 way AHD/TVI/CVI 1080P camera surveillance video coding save as a local file, support H265.

07 AHD/TVI/CVI 720P camera real-time display source 1 can be viewed through the VCA. HDMI screen real-time 8 way AHD/TVI/CVI 720P camera monitoring video

08 AHD/TV1 / CVI 720 p video camera keep real-time encoding source also will 8-way AHD TVI/CVI 720 p/surveillance camera video coding is saved as a local file, support H265 | H264 format

09 CVBS (D1) camera real-time display source code can be viewed through the VGA, HIM1 screen real-time 8-way CVBS (D1) camera surveillance video

10 CVBS (D1) camera real-time coding save source code at the same time 8-way CVBS (D1) camera monitoring video coding save as a local file, support H265,H264 format

11 1 audio function source code including audio coding save (recording) source code, audio decoding playback source code, support AAC.G711, G726,ADPCM format

12 RTSP server source code will come from the AHD camera video through the RTSP protocol (network) sent, you can use the VLC player to view 13 video decoding playback source code

14 RTSP client source code decoded H264 H265 XPEG4 format file, and through the VGA, HDMI screen play video reception from the RTSP server (usually 1PC end) network video stream, and saved as a local file

15 OSD function source code

16 Uboot source

17 Kerne1 source provide configuration changes uboot source code, can be directly compiled, burn to the development board to run | provide configuration changes the kernel source code, can be directly compiled, burn to the development board to run

18 the Busybox source | provide configuration changes the Busybox source code, can be directly compiled, burn to the development board to run

19 rootfs source files and tools | tools provide the source file and mirror

20 0T source code including 9T transplant tutorial documents, transplant good OT source code, QT GUI sample program source code

21 driver source NVP6158, NP6134, TLV320AIC31 driver source code source code

22 RTC driver source code and operation example RTC driver source code, the use of tutorial documentation

23 Idle GPIO using the documentation development board leads to the use of idle GPIO tutorial documentation

24 development board use tutorial includes development environment construction, development board use instructions, source code compilation instructions, learning materials, etc

25 Official SDK Development Kit provides Hays Official SDK Development Kit free of charge, including the original software and hardware information

The development environment has been configured to compile BSP and SAMPLE applications directly

Reference schematic diagram of PCE Hayes official development board schematic diagram, PCB source files and hardware design guide

"28 Interface Description Development Board Hardware Interface Description"

29 the commonly used tools | open software

30 4 g module (EC20) data package (optional) extra purchase alone, contains tutorial EC20 module, transplantation, using document and relevant source 31 GPS 4 g dual function module data package (optional) | extra purchase alone, 4 g dual function module includes GPS, transplant tutorials, using document and the relevant source code

32 WIFI module data package (optional) | extra purchase alone, including USB WIFI module, tutorials, transplantation using document and the relevant source code 33 infrared module data package (optional) extra purchase alone, include the infrared receiving module, infrared remote control, use the document and the relevant source code

Other information is in hot update.Note: The schematic diagram and PCB data of this board are not provided, and the related technical support of hardware design is not provided. Please refer to the official hardware information of Hayes for designing your own hardware


Hi3521DV100 is a professional SoC chip for multi-channel high-definition (1080p/720p) and multi-channel clear (DI/960H) DVR product applications.H13521DV100 has built-in ARM A7 dual-core processor and high-performance H.265/ H.264 video codec engine. It integrates high-performance video/image processing engine containing multiple complex image processing algorithms, provides HDMI/VGA high-definition display output capability, and also integrates rich peripheral interfaces.The SoC chip provides customers with a high performance, excellent image quality and low-cost analog HD /SDI1 solution, while significantly reducing the cost of EBOM related products.

Single-chip HI3521DV100 DVR solution

4x1080p DVR4x1080p@30fps H.265 encode +4x1080p @30fps H.265 encode +4x1080p @30fps H.265 decode +4x1080p@2fps JPEG encode HDMI+VGA 1080p PA60fps homology output +CVBS output 8x720p DVR8x720p@30fps H.265 encode + 8xdi@30fps H

+8x720p@30fps H.265 decoding +8x720p@2fps JPEG encoding

HDMI+VGA 1080p@60fps homologous output +CVBS output

16x720p DVR (non-real-time)16x720p@1 5FPS H.265 encoding +16xD1@15fps H.265 encoding

+16x720p@ 1 5FPS H.265 decoding +16x720p@2fps JPEG encoding

HDMI+VGA 1080pa@60fps homologous output +CVBS output

16X960H DVR16x960H@30fps H.265 code +16xCIF@30fps H.265 code

+16x960H@30fps H.265 decoding +16x960H@2fps JPEG encoding

HDMI+VGA 1080p@60fps homologous output +CVBS output


The V1 module captures video images, which can be cut, scaled and other processing, and output multi-channel image data with different resolutions.

The decoding module decodes the encoded video stream and sends the parsed image data to VPSS for image processing or directly to VO for display.Video stream in H264/MPEG4/MPEG2 format can be decoded.

The VPSS module receives the images sent by VI and decoding module, which can denoise, enhance and sharpen the image, and realize the same source output multi-channel image data with different resolutions for encoding, preview or capture.

The coding module receives image data captured by V1 and output after processing by VPSS. It can superimpose OSD images set by users through Region module, and then encode and output corresponding code streams according to different protocols.

The VDA module receives the output image of VI, carries out movement detection and occlusion detection, and finally outputs the detection analysis result.

The VO module receives the output image processed by VPSS, which can be used for playback control and other processing. Finally, the VO module outputs the image to the peripheral video device according to the output protocol configured by the user.

The AI module captures the audio data, and then the AENC module supports encoding it according to a variety of audio protocols, and finally outputs the audio code stream.

Audio stream obtained from network or peripheral storage devices can be directly sent to ADEC module. ADEC supports decoding of a variety of different audio format codestreams. After decoding, the data is sent to AO module to play the sound.



Video cache pool

Video cache pool mainly provides bulk physical memory management function to media business, is responsible for memory allocation and recovery, gives full play to the role of memory cache pool, and makes the physical memory resources be used reasonably in each media processing module.A set of cache blocks of the same size and contiguous physical addresses constitute a video cache pool.The video input channel requires the use of a common video cache pool.All video input channel can be obtained from the public video buffer pool video cache block is used to save the acquisition of image (as shown in figure 2-1 in from A public video buffer pool for video cache block Bm), because of the video input channel does not provide function of creation and destruction of public video buffer pool, therefore, before the system initialization, must configure public video buffer pool for the video input channel.Depending on the business, the number of public cache pools, the size and number of cache blocks vary.The lifetime of the cache block shown in Figure 2-1 refers to the situation where the cache block is passed through the VPSS channel to subsequent modules (solid line path in Figure 2-1). If the cache block is not passed through the VPSS channel to other modules at all, it will be put back into the public cache pool after processing by the VPSS module (dashed line path in Figure 2-1).





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